| 2026 | DATE | Multi-Partner Project: Outcomes of the ICSC Flagship 2 Project on Architectures and Design Methodologies to Accelerate AI Workloads. | Cristina Silvano, Fabrizio Ferrandi, Serena Curzel, Daniele Ielmini, Cristian Zambelli, Sebastiano Fabio Schifano, Francesco Conti, Angelo Garofalo, Luca Benini, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Fanny Spagnolo, Pasquale Corsonello, Stefania Perri, Fabio Frustaci |
| 2025 | DATE | Optimizing Qubit Assignment in Modular Quantum Systems via Attention-Based Deep Reinforcement Learning. | Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
| 2025 | PDP | An Anomaly Detection Model for RISC-V in Automotive Applications: A Domain-Specific Accelerator Perspective. | Elio Vinciguerra, Enrico Russo, Maurizio Palesi, Giuseppe Ascia |
| 2025 | QCE | TeleSABRE: Heuristic Layout Synthesis in Multi-Core Quantum Systems with Teleport Interconnect. | Enrico Russo, Elio Vinciguerra, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
| 2024 | DAC | A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems. | Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
| 2024 | ISCAS | Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. | Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania |
| 2022 | DATE | MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping. | Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
| 2021 | PERCOM | LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation. | Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
| 2020 | DSD | DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators. | Habiba Lahdhiri, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Jordane Lorandel, Emmanuelle Bourdel, Vincenzo Catania |
| 2016 | WETICE | Making Android Apps Data-Leak-Safe by Data Flow Analysis and Code Injection. | Giuseppe Ascia, Vincenzo Catania, Raffaele Di Natale, Andrea Fornaia, Misael Mongiov, Salvatore Monteleone, Giuseppe Pappalardo, Emiliano Tramontana |
| 2015 | DATE | A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. | Andrea Mineo, Mohd Shahrizal Rusli, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono |
| 2014 | DATE | An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs. | Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania |
| 2014 | ISCA | A Closed Loop Control based Power Manager for WiNoC Architectures. | Mohd Shahrizal Rusli, Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono |
| 2013 | DSD | An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip. | Giuseppe Ascia, Maurizio Palesi, Vincenzo Catania |
| 2013 | DSD | Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. | Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania |
| 2013 | HPCC | Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. | Andrea Mineo, Marina Masi, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania |
| 2012 | PPSN | A Study on Evolutionary Multi-Objective Optimization with Fuzzy Approximation for Computational Expensive Problems. | Alessandro G. Di Nuovo, Giuseppe Ascia, Vincenzo Catania |
| 2009 | DSD | Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. | Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania |
| 2006 | CEC | A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. | Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti |
| 2005 | ASPDAC | A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
| 2005 | CEC | An evolutionary approach to network-on-chip mapping problem. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi |
| 2005 | ISCAS | Hyperblock formation: a power/energy perspective for high performance VLIW architectures. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
| 2003 | CEC | An evolutionary approach for reducing the switching activity in address buses. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato |
| 2002 | INFOCOM | An efficient buffer management policy based on an integrated Fuzzy-GA approach. | Giuseppe Ascia, Vincenzo Catania, Daniela Panno |
| 2002 | VLSID | A Framework for Design Space Exploration of Parameterized VLSI Systems. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi |
| 2001 | INFOCOM | A Fuzzy Buffer Management Scheme For ATM and IP Networks. | Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Daniela Panno |
| 2001 | SAC | An adaptive fuzzy threshold scheme for high performance shared-memory switches. | Giuseppe Ascia, Vincenzo Catania, Daniela Panno |
| 1998 | VLSID | A Framework for a Parallel Architecture Dedicated to Soft Computing. | Giuseppe Ascia, Vincenzo Catania |
| 1997 | VLSID | Design of a VLSI Hardware PET Decoder. | Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili |
| 1995 | ICTAI | An efficient hardware architecture to support complex fuzzy reasoning. | Giuseppe Ascia, Vincenzo Catania |
| 1995 | LCN | Design of a VLSI fuzzy processor for ATM traffic sources management. | Giuseppe Ascia, Giuseppe Ficili, Daniela Panno |
| 1995 | VLSID | Design of a VLSI parallel processor for fuzzy computing. | Giuseppe Ascia, Vincenzo Catania |