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Greg Stitt

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

36

Venues

13

Active years

2000–2026

Best venue rank

A*

Where they publish

Papers

36 indexed papers, newest first.

YearVenueTitleAuthors
2026FPGABridging the Gap: A Module-Context Modeling Methodology for Hyperscale FPGA Applications.Madison N. Emas, Austin Baylis, Greg Stitt
2026FPGAEdgeSort: A Sub-100 ns, Line-Rate FPGA Streaming Sorter.Greg Stitt, Wesley Piard, Christopher Crary
2024FPGALow-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet.Greg Stitt, Wesley Piard, Christopher Crary
2023EUROGPUsing FPGA Devices to Accelerate Tree-Based Genetic Programming: A Preliminary Exploration with Recent Technologies.Christopher Crary, Wesley Piard, Greg Stitt, Caleb Bean, Benjamin M. Hicks
2023VTSAn Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware.Jackson Fugate, Greg Stitt, Naren Vikram Raj Masna, Aritra Dasgupta, Swarup Bhunia, Nij Dorairaj, David Kehlet
2022CASESWork-in-Progress: Toward a Robust, Reconfigurable Hardware Accelerator for Tree-Based Genetic Programming.Christopher Crary, Wesley Piard, Britton Chesley, Greg Stitt
2020SCFPGA Acceleration of Fluid-Flow Kernels.Ryan Blanchard, Greg Stitt, Herman Lam
2019DATEDynamic Scheduling on Heterogeneous Multicores.Ayobami S. Edun, Ruben Vazquez, Ann Gordon-Ross, Greg Stitt
2019ICCDEnergy Prediction for Cache Tuning in Embedded Systems.Ruben Vazquez, Ann Gordon-Ross, Greg Stitt
2018FCCMHigh-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlex.Madison N. Emas, Austin Baylis, Greg Stitt
2018FPGAScalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems.Greg Stitt, Abhay Gupta, Madison N. Emas, David Wilson, Austin Baylis
2018ICPPScalable Behavioral Emulation of Extreme-Scale Systems Using Structural Simulation Toolkit.Ajay Ramaswamy, Nalini Kumar, Aravind Neelakantan, Herman Lam, Greg Stitt
2016FPGADoubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining (Abstract Only).Aaron Landy, Greg Stitt
2015FCCMAdjustable-Cost Overlays for Runtime Compilation.James Coole, Greg Stitt
2015FCCMRevisiting Serial Arithmetic: A Performance and Tradeoff Analysis for Parallel Applications on Modern FPGAs.Aaron Landy, Greg Stitt
2014FCCMA High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector Multiplication.Jeremy Fowers, Kalin Ovtcharov, Karin Strauss, Eric S. Chung, Greg Stitt
2014SCOPESA framework for dynamic parallelization of FPGA-accelerated applications.Jeremy Fowers, Jianye Liu, Greg Stitt
2013FPGAA high-performance, low-energy FPGA accelerator for correntropy-based feature tracking (abstract only).Patrick Cooke, Jeremy Fowers, Lee Hunt, Greg Stitt
2013FPGADynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations.Jeremy Fowers, Greg Stitt
2012CASESA low-overhead interconnect architecture for virtual reconfigurable fabrics.Aaron Landy, Greg Stitt
2012CASESThe RACECAR heuristic for automatic function specialization on multi-core heterogeneous systems.John Robert Wernsing, Greg Stitt, Jeremy Fowers
2012FPGACommunication visualization for bottleneck detection of high-level synthesis applications.John Curreri, Greg Stitt, Alan D. George
2012FPGAA performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications.Jeremy Fowers, Greg Brown, Patrick Cooke, Greg Stitt
2012FPGAVirtualRC: a virtual FPGA platform for applications and tools portability.Robert Kirchgessner, Greg Stitt, Alan D. George, Herman Lam
2012PPoPPRACECAR: a heuristic for automatic function specialization on multi-core heterogeneous systems.John Robert Wernsing, Greg Stitt
2009SCSCF: a device- and language-independent task coordination framework for reconfigurable, heterogeneous systems.Vikas Aggarwal, Rafael Garca, Greg Stitt, Alan D. George, Herman Lam
2009SCBridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+.Vikas Aggarwal, Alan D. George, Kishore Yalamanchili, Changil Yoon, Herman Lam, Greg Stitt
2009SCA framework for core-level modeling and design of reconfigurable computing algorithms.Gongyu Wang, Greg Stitt, Herman Lam, Alan D. George
2008FPGAC is for circuits: capturing FPGA circuits as sequential code for portability.Scott Sirowy, Greg Stitt, Frank Vahid
2006ICCADA code refinement methodology for performance-improved synthesis from C.Greg Stitt, Frank Vahid, Walid A. Najjar
2005DATEA Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms.Greg Stitt, Frank Vahid
2005FPGATechniques for synthesizing binaries to an advanced register/memory structure.Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
2003DACDynamic hardware/software partitioning: a first approach.Greg Stitt, Roman L. Lysecky, Frank Vahid
2002FCCMUsing On-Chip Configurable Logic to Reduce Embedded System Software Energy.Greg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid
2002ICCADHardware/software partitioning of software binaries.Greg Stitt, Frank Vahid
2000CASESA first-step towards an architecture tuning methodology for low power.Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky