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Greg Yeric

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

12

Venues

6

Active years

2007–2017

Best venue rank

A*

Where they publish

Papers

12 indexed papers, newest first.

YearVenueTitleAuthors
2017ICCADStandard cell library design and optimization methodology for ASAP7 PDK: (Invited paper).Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
2017ICCDDTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node.Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan
2017ISLPEDFrequency and time domain analysis of power delivery network for monolithic 3D ICs.Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2016DACMatch-making for monolithic 3D IC: finding the right technology node.Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2016ICCADCascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools.Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim
2016ISLPEDFour-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study.Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2015ISLPEDPower benefit study of monolithic 3D IC at the 7nm technology node.Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2014ITCDesign, technology and yield in the post-moore era.Greg Yeric
2012DACExploring sub-20nm FinFET design with predictive technology models.Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao
2012ISLPEDDesign benchmarking to 7nm with FinFET predictive technology models.Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao
2011DATECorrelating models and silicon for improved parametric yield.Rob Aitken, Greg Yeric, David Flynn
2007DACMaking Manufacturing Work For You.Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian