Hailong Cui
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
3
Active years
2002–2016
Best venue rank
National
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | FUSION | A time-varying clutter intensity estimation algorithm by using Gibbs sampler and BIC. | Weifeng Liu, Hailong Cui, Chenglin Wen |
| 2007 | ITC | Verification and debugging of IDDQ test of low power chips. | Michael Laisne, Triphuong Nguyen, Songlin Zuo, Xiangdong Pan, Hailong Cui, Cher Bai, A. Street, M. Parley, Neetu Agrawal, K. Sundararaman |
| 2007 | VLSID | Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. | Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov |
| 2002 | VLSID | A Novel Method to Improve the Test Efficiency of VLSI Tests. | Hailong Cui, Sharad C. Seth, Shashank K. Mehta |