| 2016 | DAC | VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency. | Hadi Asghari Moghaddam, Hamid Reza Ghasemi, Abhishek Arvind Sinkar, Indrani Paul, Nam Sung Kim |
| 2015 | ICCD | Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications. | Hamid Reza Ghasemi, Ulya R. Karpuzcu, Nam Sung Kim |
| 2012 | DAC | Cost-effective power delivery to support per-core voltage domains for power-constrained processors. | Hamid Reza Ghasemi, Abhishek A. Sinkar, Michael J. Schulte, Nam Sung Kim |
| 2011 | HPCA | Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors. | Hamid Reza Ghasemi, Stark C. Draper, Nam Sung Kim |
| 2010 | ICCD | Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC. | Shi-Ting Zhou, Sumeet Katariya, Hamid Reza Ghasemi, Stark C. Draper, Nam Sung Kim |
| 2010 | ISLPED | Workload-adaptive process tuning strategy for power-efficient multi-core processors. | Jungseob Lee, Chi-Chao Wang, Hamid Reza Ghasemi, Lloyd Bircher, Yu Cao, Nam Sung Kim |
| 2008 | CSICC | High Performance Mathematical Quarter-Pixel Motion Estimation with Novel Rate Distortion Metric for H.264/AVC. | Somayeh Sardashti, Hamid Reza Ghasemi, Mehdi Semsarzadeh, Mahmoud Reza Hashemi |
| 2005 | VLSID | An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. | Hamid Reza Ghasemi, Zainalabedin Navabi |