| 2012 | DSD | SUT-RNS Residue-to-Binary Converters Design. | Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos |
| 2011 | DSD | Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion. | Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos |
| 2010 | DSD | Area-Efficient Multi-moduli Squarers for RNS. | Dimitris Bakalis, Haridimos T. Vergos |
| 2008 | DSD | On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. | Haridimos T. Vergos, Dimitris Bakalis |
| 2007 | DSD | An Efficient BIST Scheme for Non-Restoring Array Dividers. | Haridimos T. Vergos |
| 2006 | DSD | Novel Modulo 2 | Haridimos T. Vergos, Costas Efstathiou |
| 2005 | RSP | KoVer: A Sophisticated Residue Arithmetic Core Generator. | Nikolaos Kostaras, Haridimos T. Vergos |
| 2004 | DSD | Diminished-1 Modulo 2 | Haridimos T. Vergos, Costas Efstathiou |
| 2003 | IOLTS | An Efficient BIST scheme for High-Speed Adders. | Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou |
| 2003 | ISCAS | A systematic methodology for designing area-time efficient parallel-prefix modulo 2 | Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou |
| 2003 | ISCAS | Efficient BIST schemes for RNS datapaths. | Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou |
| 2001 | ARITH | High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. | Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou |
| 1999 | DATE | Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. | Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas |
| 1999 | EDCC | Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. | Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos |
| 1996 | EDCC | On the Yield of VLSI Processors with on-chip CPU Cache. | Dimitris Nikolos, Haridimos T. Vergos |