Harry Hsieh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
14
Venues
4
Active years
1995–2009
Best venue rank
A*
Where they publish
Papers
14 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2009 | ASPDAC | Partial order method for timed simulation of system-level MPSoC designs. | Eric Cheung, Harry Hsieh, Felice Balarin |
| 2009 | ASPDAC | Fast and accurate performance simulation of embedded software for MPSoC. | Eric Cheung, Harry Hsieh, Felice Balarin |
| 2009 | ASPDAC | Memory subsystem simulation in software TLM/T models. | Eric Cheung, Harry Hsieh, Felice Balarin |
| 2006 | DATE | Communication and co-simulation infrastructure for heterogeneous system integration. | Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli |
| 2005 | DAC | Simulation based deadlock analysis for system level designs. | Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe |
| 2005 | DATE | System Synthesis for Networks of Programmable Blocks. | Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid |
| 2005 | DATE | Assertion-Based Design Exploration of DVS in Network Processor Architectures. | Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin |
| 2004 | DATE | Utilizing Formal Assertions for System Design of Network Processors. | Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin |
| 2003 | DAC | Automatic trace analysis for logic of constraints. | Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe |
| 2003 | DATE | Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. | Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe |
| 2000 | DAC | Efficient methods for embedded system design space exploration. | Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
| 1999 | ICCAD | Synchronous equivalence for embedded systems: a tool for design exploration. | Harry Hsieh, Felice Balarin |
| 1996 | DAC | Formal Verification of Embedded Systems based on CFSM Networks. | Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
| 1995 | DAC | Synthesis of Software Programs for Embedded Control Applications. | Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Luciano Lavagno, Harry Hsieh, Kei Suzuki, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich |