Haruyoshi Yonekawa
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2017–2018
Best venue rank
A
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | FPGA | A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. | Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato |
| 2017 | FPGA | A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). | Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura |
| 2017 | FPL | A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA. | Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato |