| 2026 | ASPDAC | Standard Cell Layout Generation: Methodological Evolution and Architectural Impacts. | Junghyun Yoon, Ikkyum Kim, Gyumin Kim, Sojung Park, Heechun Park |
| 2026 | ASPDAC | SMT-Based Optimal Transistor Folding and Placement for Standard Cell Layout Generation. | Junghyun Yoon, Heechun Park |
| 2026 | DATE | Critical-Path-Centric 3D IC Placement for Timing Optimization. | Sojung Park, Heechun Park |
| 2026 | DATE | Breaking Standard Cell Margin Constraints for Area-Efficient VLSI Design. | Junghyun Yoon, Jooyeon Jeong, Heechun Park |
| 2026 | ISLPED | Congestion-Aware Integrated Optimization of Multi-Bit Flip-Flop Clustering and Placement. | Jiyun Ham, Heechun Park |
| 2026 | ISLPED | BS-CSO: Backside-Assisted Clock-Signal Co-Optimization Framework. | Ikkyum Kim, Geonhyeong Park, Heechun Park |
| 2026 | ISLPED | Post-Placement Optimization with Pin-Level Graph Isomorphism Network and Recurrent Q-Learning. | Kijung Kong, Heechun Park |
| 2025 | ASPDAC | PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation. | Eunsol Jeong, Taewhan Kim, Heechun Park |
| 2025 | ASPDAC | Clustering-Driven Bonding Terminal Legalization with Reinforcement Learning for F2F 3D ICs. | Gyumin Kim, Heechun Park |
| 2025 | DAC | Mitigating Routability Problems in Complementary-FET-based VLSI Designs. | Junghyun Yoon, Heechun Park |
| 2025 | DATE | Timing-Driven Detailed Placement with Unsupervised Graph Learning. | Dhoui Lim, Heechun Park |
| 2025 | ICCAD | A Unified Design Flow for Homogeneous and Heterogeneous 3D Integration with Fine-Pitch Hybrid Bonding. | Gyumin Kim, Heechun Park |
| 2025 | ISLPED | Timing-Driven Macro Placement with Connectivity-Aware Clustering. | Gangmin Jeon, Heechun Park |
| 2024 | ICCD | Memristive Logic-in-Memory Implementation with Area Efficiency and Parallelism. | Ikkyum Kim, Heechun Park |
| 2023 | DATE | DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. | Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim |
| 2022 | DATE | A Systematic Removal of Minimum Implant Area Violations under Timing Constraint. | Eunsol Jeong, Heechun Park, Taewhan Kim |
| 2022 | ISLPED | Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. | Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park |
| 2019 | DAC | Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse. | Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim |
| 2019 | DAC | RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs. | Heechun Park, Kyungwook Chang, Bon Woong Ku, Jinwoo Kim, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Saibal Mukhopadhyay, Krishnendu Chakrabarty, Sung Kyu Lim |
| 2019 | ETS | Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs. | Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Bon Woong Ku, Krishnendu Chakrabarty, Sung Kyu Lim |
| 2018 | DATE | Structure optimizations of neuromorphic computing architectures for deep neural network. | Heechun Park, Taewhan Kim |
| 2013 | ICCAD | Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees. | Heechun Park, Taewhan Kim |