Henry H. Y. Chan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2007–2007
Best venue rank
A*
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2007 | DAC | Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. | Henry H. Y. Chan, Zeljko Zilic |
| 2007 | ISCAS | A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits. | Henry H. Y. Chan, Zeljko Zilic |