| 2021 | ICCE | Supporting System to Encourages Self-review in Composition Class - Investigation into the Learner's Reaction. | Yan Zhao, Haruhiko Takasa, Hidehiko Kita |
| 2019 | KES | Spiking Neural Network to Extract Frequent Words from Japanese Speech Data. | Kenta Morita, Haruhiko Takase, Naoki Morita, Hiroharu Kawanaka, Hidehiko Kita |
| 2017 | ICCE | A Collaborative Learning Method of Learning from Errors in Japanese Writing. | Li Zhang, Hidehiko Kita |
| 2009 | IJCNN | Obstacle to training SpikeProp networks - Cause of surges in training process -. | Haruhiko Takase, Masaru Fujita, Hiroharu Kawanaka, Shinji Tsuruoka, Hidehiko Kita, Terumine Hayashi |
| 2008 | IJCNN | Shape of error surfaces in SpikeProp. | Masaru Fujita, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi |
| 2007 | ICCE | Descriptive Answer Clustering System for Immediate Feedback. | Kazutaka Noro, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi, Naoki Morita |
| 2007 | IJCNN | Enhancing both generalization and fault tolerance of multilayer neural networks. | Haruhiko Takase, Masahiko Masahiko, Hidehiko Kita, Terumine Hayashi |
| 2006 | IJCNN | Fault tolerant training algorithm for multi-layer neural networks focused on hidden unit activities. | Haruhiko Takase, Hidehiko Kita, Terumine Hayashi |
| 2005 | IJCNN | Dynamic construction of fault tolerant multi-layer neural networks. | Haruhiko Takase, Ayumi Nobuto, Hidehiko Kita, Terumine Hayashi |
| 2004 | ASPDAC | Test data compression technique using selective don't-care identification. | Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase |
| 2004 | IJCNN | A study on the simple penalty term to the error function from the viewpoint of fault tolerant training. | Haruhiko Takase, Hidehiko Kita, Terumine Hayashi |
| 2003 | IJCNN | Effect of regularization term upon fault tolerant training. | Haruhiko Takase, Hidehiko Kita, Tetumine Hayashi |
| 2000 | IJCNN | Evaluation Function for Fault Tolerant Multi-Layer Neural Networks. | Haruhiko Takase, Tsuyoshi Shinogi, Terumine Hayashi, Hidehiko Kita |
| 1997 | ASPDAC | An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits. | Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita |