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Hideki Ando

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

16

Venues

4

Active years

1993–2026

Best venue rank

A*

Where they publish

Papers

16 indexed papers, newest first.

YearVenueTitleAuthors
2026ISCAHierarchical Wakeup Logic of the Issue Queue for High Scalability.Hideki Ando, Hajime Shimada
2024MICROLocalizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue.Kenichiro Mori, Sota Kosugi, Hiroto Yoshida, Hajime Shimada, Hideki Ando
2022ICCDSegmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area.Hideki Ando
2019MICROSWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue.Hideki Ando
2018ICCDRearranging Random Issue Queue with High IPC and Short Delay.Shinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando
2018MICROPerformance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices.Hideki Ando
2014ICCDEnergy efficiency improvement of renamed trace cache through the reduction of dependent path length.Ryota Shioya, Hideki Ando
2014MICROA Front-End Execution Architecture for High Energy Efficiency.Ryota Shioya, Masahiro Goshima, Hideki Ando
2013MICROMLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP.Yuya Kora, Kyohei Yamaguchi, Hideki Ando
2011ICCDEvaluation of issue queue delay: Banking tag RAM and identifying correct critical path.Kyohei Yamaguchi, Yuya Kora, Hideki Ando
2009ICCDReducing register file size through instruction pre-execution enhanced by value prediction.Yusuke Tanaka, Hideki Ando
2003ISLPEDPipeline stage unification: a low-energy consumption technique for future mobile processors.Hajime Shimada, Hideki Ando, Toshio Shimada
2002ISLPEDA preactivating mechanism for a VT-CMOS cache using address prediction.Ryo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada
1996ISCAPerformance Comparison of ILP Machines with Cycle Time Evaluation.Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya
1995ISCAUnconstrained Speculative Execution with Predicated State Buffering.Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya
1993ICCDSpeculative Execution and Reducing Branch Penalty in a Parallel Issue Machine.Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya