Hideto Hidaka
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
1
Active years
1986–2002
Best venue rank
A
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2002 | ITC | A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. | Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo |
| 2000 | ITC | A built-in self-repair analyzer (CRESTA) for embedded DRAMs. | Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka |
| 1992 | ITC | A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. | Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima |
| 1986 | ITC | Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode. | Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima, Y. Hayasaka |