Hiroshi Iwata
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2010–2010
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | DDECS | A synthesis method to propagate false path information from RTL to gate level. | Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara |
| 2010 | ETS | Test pattern selection to optimize delay test quality with a limited size of test set. | Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara |