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Hossein Asadi

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

34

Venues

15

Active years

2005–2026

Best venue rank

A*

Where they publish

Papers

34 indexed papers, newest first.

YearVenueTitleAuthors
2026ISPASSCharacterization and Performance Analysis of Aging Effect on Enterprise HDDs.Ava Dezhban, Mohammadamin Ajdari, Hossein Asadi
2026ISPASSDo Not Get Fooled: Use True Device Utilization on High-Performance Storage Devices.Ali Sedaghatgoo, Mohammadamin Ajdari, Erfan Teymouri, Hossein Asadi
2026SIGMETRICSTowards Scalable Storage Architectures for GPU Clusters Running Large Language Models.Ali Sedaghatgoo, Reza Salkhordeh, Andr Brinkmann, Hossein Asadi
2025EDBTNo Time to Halt: In-Situ Analysis for Large-Scale Data Processing via Virtual Snapshotting.Reza Salkhordeh, Felix Martin Schuhknecht, Hossein Asadi, Steffen Eiden, Andr Brinkmann
2025PDPEnhancing mmap scalability by saving TLB shootdowns during page recycling.Frederic Schimmelpfennig, Andr Brinkmann, Hossein Asadi, Reza Salkhordeh
2023ASPLOSRe-architecting I/O Caches for Emerging Fast Storage Devices.Mohammadamin Ajdari, Pouria Peykani Sani, Amirhossein Moradi, Masoud Khanalizadeh Imani, Amir Hossein Bazkhanei, Hossein Asadi
2022SIGMETRICSAn Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems.Mohammadamin Ajdari, Patrick Raaf, Mostafa Kishani, Reza Salkhordeh, Hossein Asadi, Andr Brinkmann
2020DATESTAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation.Mostafa Hadizadeh, Elham Cheshmikhani, Hossein Asadi
2019ASPDACROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches.Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
2019DATELBICA: A Load Balancer for I/O Cache Architectures.Saba Ahmadian, Reza Salkhordeh, Hossein Asadi
2019DATEEnhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation.Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
2018DATEInvestigating power outage effects on reliability of solid-state drives.Saba Ahmadian, Farhad Taheri, Mehrshad Lotfi, Maryam Karimi, Hossein Asadi
2018SIGMETRICSECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms.Saba Ahmadian, Onur Mutlu, Hossein Asadi
2017DATEEvaluating impact of human errors on the availability of data storage systems.Mostafa Kishani, Reza Eftekhari, Hossein Asadi
2017DATEA power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era.Zeinab Seifoori, Behnam Khaleghi, Hossein Asadi
2016DATEAn Operating System level data migration scheme in hybrid DRAM-NVM memory architecture.Reza Salkhordeh, Hossein Asadi
2016FPLStress-aware routing to mitigate aging effects in SRAM-based FPGAs.Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jrg Henkel, Hossein Asadi
2015FPLAn efficient reconfigurable architecture by characterizing most frequent logic functions.Iman Ahmadpour, Behnam Khaleghi, Hossein Asadi
2015SIGMETRICSDiskAccel: Accelerating Disk-Based Experiments by Representative Sampling.Mojtaba Tarihi, Hossein Asadi, Hamid Sarbazi-Azad
2014DATEA power-efficient reconfigurable architecture using PCM configuration technology.Ali Ahari, Hossein Asadi, Behnam Khaleghi, Mehdi Baradaran Tahoori
2014FPLTowards dark silicon era in FPGAs using complementary hard logic design.Ali Ahari, Behnam Khaleghi, Zahra Ebrahimi, Hossein Asadi, Mehdi Baradaran Tahoori
2013ASPDACCLASS: Combined logic and architectural soft error sensitivity analysis.Mojtaba Ebrahimi, Liang Chen, Hossein Asadi, Mehdi Baradaran Tahoori
2013DACA layout-based approach for multiple event transient analysis.Mojtaba Ebrahimi, Hossein Asadi, Mehdi Baradaran Tahoori
2013DSNFTSPM: A Fault-Tolerant ScratchPad Memory.Amir Mahdi Hosseini Monazzah, Hamed Farbeh, Seyed Ghassem Miremadi, Mahdi Fazeli, Hossein Asadi
2011DATEScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications.Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi
2011DATESoft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs).Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori
2010DSDA Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits.Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori
2010DSNA fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design.Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Seyed Nematollah Ahmadian
2010PRDCSystem-Level Vulnerability Estimation for Data Caches.Alireza Haghdoost, Hossein Asadi, Amirali Baniasadi
2007VTSCase Study: Soft Error Rate Analysis in Storage Systems.Brian Mullins, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli, Kevin Granlund, Rudy Bauer, Scott Romano
2006DATEVulnerability analysis of L2 cache elements to single event upsets.Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli
2006ICCADSoft error derating computation in sequential circuits.Hossein Asadi, Mehdi Baradaran Tahoori
2006ISCASSoft error hardening for logic-level designs.Hossein Asadi, Mehdi Baradaran Tahoori
2005ISPASSBalancing Performance and Reliability in the Memory Hierarchy.Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli