Hubert Kaeslin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
16
Venues
9
Active years
1988–2015
Best venue rank
A*
Where they publish
Papers
16 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | VCIP | Automatic multiview synthesis - Towards a mobile system on a chip. | Michael Schaffner, Frank K. Grkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic |
| 2015 | VCIP | Automatic multiview synthesis - Prototype demo. | Michael Schaffner, Frank K. Grkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic |
| 2014 | DAC | An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing. | Michael Schaffner, Frank K. Grkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini |
| 2014 | ISCAS | Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers. | Christoph Keller, Frank K. Grkaynak, Hubert Kaeslin, Norbert Felber |
| 2013 | ISCAS | Live demonstration: Real-time audio restoration using sparse signal recovery. | David E. Bellasi, Patrick Maechler, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer |
| 2012 | ISCAS | Hardware-efficient random sampling of fourier-sparse signals. | Patrick Maechler, Norbert Felber, Hubert Kaeslin, Andreas Burg |
| 2006 | DAC | Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. | Felix Brgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner |
| 2006 | DATE | Two-phase resonant clocking for ultra-low-power hearing aid applications. | Flavio Carbognani, Felix Brgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
| 2006 | ISCAS | 42% power savings through glitch-reducing clocking strategy in a hearing aid application. | Flavio Carbognani, Felix Brgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
| 2003 | ISCAS | Variable delay ripple carry adder with carry chain interrupt detection. | Andreas Burg, Frank K. Grkaynak, Hubert Kaeslin, Wolfgang Fichtner |
| 2002 | CHES | 2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. | Adrian K. Lutz, Jrg Treichler, Frank K. Grkaynak, Hubert Kaeslin, Grard Basler, Antonia Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner |
| 1999 | ITC | Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. | Manfred Stadler, Thomas Rwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann |
| 1996 | PPSN | Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits. | Robert Rogenmoser, Hubert Kaeslin, Tobias Blickle |
| 1993 | ITC | VINCI: Secure Test of a VLSI High-Speed Encryption System. | Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Reto Zimmermann, Wolfgang Fichtner |
| 1991 | ICCD | VLSI Implementation of a New Block Cipher. | Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai |
| 1988 | WG | Application of Graph Theory to Topology Generation for Logic Gates. | Hubert Kaeslin |