Indira Nair
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
5
Active years
1986–2012
Best venue rank
A
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | DATE | Power management of multi-core chips: Challenges and pitfalls. | Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta Sharma Gupta, Michael B. Healy, Hans M. Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger |
| 2008 | ASPDAC | Exploring power management in multi-core systems. | Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer |
| 2004 | CASES | An efficient system-on-a-chip design methodology for networking applications. | Valentina Salapura, Christos J. Georgiou, Indira Nair |
| 1994 | ICCD | Architectural Verification of Processors Using Symbolic Instruction Graphs. | Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen |
| 1992 | ITC | A Small Test Generator for Large Designs. | Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy |
| 1986 | ITC | Efficient Fault Simulation of CMOS Circuits with Accurate Models. | Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman |