Ireneusz Janiszewski
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2001–2004
Best venue rank
A*
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2004 | FPL | FPGA-Efficient Hybrid LUT/CORDIC Architecture. | Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe |
| 2001 | DAC | VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers. | Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth |