| 2025 | DSN | Reasoning with Happens-Before Relations About Concurrent Programs in the THETA Framework. | Csand Telbisz, Levente Bajczi, Dniel Szekeres, Andrs Vrs, Istvn Majzik |
| 2023 | FMICS | Configurable Model-Based Test Generation for Distributed Controllers Using Declarative Model Queries and Model Checkers. | Bence Graics, Vince Molnr, Istvn Majzik |
| 2022 | MODELS | System architecture synthesis for performability by logic solvers. | Mt Fldik, Kristf Marussy, Dniel Varr, Istvn Majzik |
| 2021 | EDCC | Tensor-based reliability analysis of complex static fault trees. | Dniel Szekeres, Kristf Marussy, Istvn Majzik |
| 2019 | MODELS | Towards System-Level Testing with Coverage Guarantees for Autonomous Vehicles. | Istvn Majzik, Oszkr Semerth, Csaba Hajdu, Kristf Marussy, Zoltn Szatmri, Zoltn Micskei, Andrs Vrs, Aren A. Babikian, Dniel Varr |
| 2018 | ICSE | The Gamma statechart composition framework: : design, verification and code generation for component-based reactive systems. | Vince Molnr, Bence Graics, Andrs Vrs, Istvn Majzik, Dniel Varr |
| 2018 | ISoLA | A Proposal of an Example and Experiments Repository to Foster Industrial Adoption of Formal Methods. | Rupert Schlick, Michael Felderer, Istvn Majzik, Roberto Nardone, Alexander Raschke, Colin F. Snook, Valeria Vittorini |
| 2017 | FMCAD | Theta: A framework for abstraction refinement-based model checking. | Tams Tth, kos Hajdu, Andrs Vrs, Zoltn Micskei, Istvn Majzik |
| 2016 | FORTE | A Configurable CEGAR Framework with Interpolation-Based Refinements. | kos Hajdu, Tams Tth, Andrs Vrs, Istvn Majzik |
| 2016 | INDIN | PLC code generation based on a formal specification language. | Dniel Darvas, Enrique Blanco Viuela, Istvn Majzik |
| 2016 | IFM | Formal Verification of Safety PLC Based Control Software. | Dniel Darvas, Istvn Majzik, Enrique Blanco Viuela |
| 2013 | DEPCoS | K-Induction Based Verification of Real-Time Safety Critical Systems. | Tams Tth, Andrs Vrs, Istvn Majzik |
| 2013 | SAFECOMP | Scenario-based Automated Evaluation of Test Traces of Autonomous Systems. | Gergo Hornyi, Zoltn Micskei, Istvn Majzik |
| 2011 | ICINCO | Ontology-based Test Data Generation using Metaheuristics. | Zoltn Szatmri, Jnos Olh, Istvn Majzik |
| 2011 | SSBSE | Search-Based Functional Test Data Generation Using Data Metamodel. | Jnos Olh, Istvn Majzik |
| 2009 | DEPCoS | A Model Based Framework for Specifying and Executing Fault Injection Experiments. | Jnos Olh, Istvn Majzik |
| 2009 | DSN | From assessment to standardised benchmarking: Will it happen? What could we do about it? | Henrique Madeira, Istvn Majzik |
| 2008 | DEPCoS | A Resilient SIL 2 Driver Machine Interface for Train Control Systems. | Andrea Ceccarelli, Istvn Majzik, Danilo Iovino, Fausto Caneschi, Gergely Pintr, Andrea Bondavalli |
| 2008 | DSN | International Workshop on Resilience Assessment and Dependability Benchmarking (RADB 2008). | Andrea Bondavalli, Istvn Majzik, Aad P. A. van Moorsel |
| 2007 | SAFECOMP | Development of Model Based Tools to Support the Design of Railway Control Applications. | Istvn Majzik, Zoltn Micskei, Gergely Pintr |
| 2006 | DEPCoS | Model-based Automatic Test Generation for Event-Driven Embedded Systems using Model Checkers. | Zoltn Micskei, Istvn Majzik |
| 2005 | EDCC | A Data Mining Approach to Identify Key Factors in Dependability Experiments. | Gergely Pintr, Henrique Madeira, Marco Vieira, Istvn Majzik, Andrs Pataricza |
| 2004 | ICSE | Runtime Verification of Statechart Implementations. | Gergely Pintr, Istvn Majzik |
| 2004 | ISORC | UML Based Design of Time Triggered Systems. | Istvn Majzik, Gergely Pintr, Pter Tams Kovcs |
| 2002 | EDCC | Towards Dependability Modeling of FT-CORBA Architectures. | Istvn Majzik, Gbor Huszerl |
| 2002 | ICSE | Stochastic Dependability Analysis of System Architecture Based on UML Models. | Istvn Majzik, Andrs Pataricza, Andrea Bondavalli |
| 2001 | SAFECOMP | Checking General Safety Criteria on UML Statecharts. | Zsigmond Pap, Istvn Majzik, Andrs Pataricza |
| 1999 | ISORC | Automated Dependability Analysis of UML Designs. | Andrea Bondavalli, Ivan Mura, Istvn Majzik |
| 1994 | EDCC | Hierarchical Checking of Multiprocessors Using Watchdog Processors. | Istvn Majzik, Andrs Pataricza, Mario Dal Cin, Wolfgang Hohl, Joachim Hnig, Volkmar Sieh |