| 2024 | EuroPar | Computing DTWs on CPU, GPU and FPGA with SYCL. | Cristian Campos, Rafael Asenjo, Javier Hormigo, Angeles G. Navarro |
| 2021 | ARITH | FPGA acceleration of bit-true simulations for word-length optimization. | Javier Hormigo, Gabriel Caffarena |
| 2020 | ARITH | Floating-Point Fused Multiply-Add under HUB Format. | Javier Hormigo, Julio Villalba-Moreno, Sonia Gonzalez-Navarro |
| 2019 | ARITH | Reproducible Summation Under HUB Format. | Julio Villalba-Moreno, Javier Hormigo, Francisco J. Jaime |
| 2017 | ARITH | Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems. | Sonia Gonzlez-Navarro, Javier Hormigo |
| 2017 | ICCD | Floating Point Square Root under HUB Format. | Julio Villalba-Moreno, Javier Hormigo |
| 2014 | ACSSC | Optimizing DSP circuits by a new family of arithmetic operators. | Javier Hormigo, Julio Villalba |
| 2013 | ICCD | Efficient floating-point representation for balanced codes for FPGA devices. | Julio Villalba, Javier Hormigo, Francisco Corbera, Mario A. Gonzlez, Emilio L. Zapata |
| 2008 | DSD | SIMD Enhancements for a Hough Transform Implementation. | Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata |
| 2008 | ICIP | New SIMD instructions set for image processing applications enhancement. | Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata |
| 2006 | FPL | Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. | Joaqun Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata |
| 2004 | FPL | Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. | Joaqun Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides |
| 1999 | ARITH | Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. | Javier Hormigo, Julio Villalba, Emilio L. Zapata |