Jay Schleicher
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
1998–2007
Best venue rank
A
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2007 | FPL | Equivalence Verification of FPGA and Structured ASIC Implementations. | Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam |
| 2006 | DATE | A methodology for FPGA to structured-ASIC synthesis and verification. | Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo |
| 2005 | FPGA | The Stratix II logic and routing architecture. | David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose |
| 2004 | FPL | Improving FPGA Performance and Area Using an Adaptive Logic Module. | Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini |
| 2002 | FPGA | Interconnect enhancements for a high-speed PLD architecture. | Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev |
| 1998 | FPGA | Optimizations for a Highly Cost-Efficient Programmable Logic Architecture. | Kerry Veenstra, Bruce Pedersen, Jay Schleicher, Chiakang Sung |