Jayesh Wadekar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2016–2016
Best venue rank
National
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | VLSID | A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. | Jayesh Wadekar, Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Nayak |