| 2023 | DSD | Asynchronous Circuit Design in Chisel Using Phase-Decoupled Click Elements. | Kasper Hesse, Tjark Petersen, Jens Spars |
| 2023 | ISCAS | A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks. | Zuzana Jelcicov, Evangelia Kasapaki, Oskar Andersson, Jens Spars |
| 2021 | ETFA | Evaluating a Time-Triggered Runtime System by Distributing a Flight Controller. | Eleftherios Kyriakakis, Jens Spars, Martin Schoeberl |
| 2021 | ISORC | Synchronizing Real-Time Tasks in Time-Triggered Networks. | Eleftherios Kyriakakis, Jens Spars, Peter P. Puschner, Martin Schoeberl |
| 2020 | ACSSC | A Neural Network Engine for Resource Constrained Embedded Systems. | Zuzana Jelcicov, Adrian Mardari, Oskar Andersson, Evangelia Kasapaki, Jens Spars |
| 2020 | EMSOFT | Synchronizing Real-Time Tasks in Time-Aware Networks: Work-in-Progress. | Eleftherios Kyriakakis, Jens Spars, Peter P. Puschner, Martin Schoeberl |
| 2019 | DATE | Scratchpad Memories with Ownership. | Martin Schoeberl, Trur Biskopst Strm, Oktay Baris, Jens Spars |
| 2019 | ISORC | Demonstration of a Time-predictable Flight Controller on a Multicore Processor. | Oktay Baris, Shibarchi Majumder, Trur Biskopst Strm, Anders la Cour-Harbo, Jens Spars, Thomas Bak, Martin Schoeberl |
| 2019 | ISORC | A Time-predictable TTEthenet Node. | Maja Lund, Luca Pezzarossa, Jens Spars, Martin Schoeberl |
| 2019 | MICRO | S4NOC: a minimalistic network-on-chip for real-time multicores. | Martin Schoeberl, Luca Pezzarossa, Jens Spars |
| 2018 | RTNS | Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol. | Eleftherios Kyriakakis, Jens Spars, Martin Schoeberl |
| 2017 | ISORC | A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems. | Luca Pezzarossa, Martin Schoeberl, Jens Spars |
| 2016 | PDP | Avionics Applications on a Time-Predictable Chip-Multiprocessor. | Andr Rocha, Cludio Silva, Rasmus Bo Srensen, Jens Spars, Martin Schoeberl |
| 2016 | RTNS | State-based Communication on Time-predictable Multicore Processors. | Rasmus Bo Srensen, Martin Schoeberl, Jens Spars |
| 2015 | ISORC | Models of Communication for Multicore Processors. | Martin Schoeberl, Rasmus Bo Srensen, Jens Spars |
| 2015 | ISORC | Message Passing on a Time-predictable Multicore Processor. | Rasmus Bo Srensen, Wolfgang Puffitsch, Martin Schoeberl, Jens Spars |
| 2014 | ISORC | A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip. | Rasmus Bo Srensen, Jens Spars, Mark Ruvald Pedersen, Jaspur Hojgaard |
| 2013 | DATE | An area-efficient network interface for a TDM-based network-on-chip. | Jens Spars, Evangelia Kasapaki, Martin Schoeberl |
| 2013 | DSD | Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip. | Evangelia Kasapaki, Jens Spars, Rasmus Bo Srensen, Kees Goossens |
| 2007 | DATE | A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. | Tobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Spars |
| 2006 | DSD | Packetizing OCP Transactions in the MANGO Network-on-Chip. | Tobias Bjerregaard, Jens Spars |
| 2006 | DSD | A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. | Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Spars, Johnny Halkjr Pedersen |
| 2005 | DATE | A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. | Tobias Bjerregaard, Jens Spars |
| 2005 | DATE | A Network Traffic Generator Model for Fast Network-on-Chip Simulation. | Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grndahl Olsen, Jens Spars, Jan Madsen |
| 2004 | DSD | Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. | Sune Fallgaard Nielsen, Jens Spars, Jan Madsen |
| 2002 | ISLPED | Future directions in clocking multi-ghz systems. | Vojin G. Oklobdzija, Jens Spars |