Jerome Quartana
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2002–2005
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | FPL | GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. | Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin |
| 2002 | DATE | High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. | Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana |