| 2026 | ACL | Bridging the Temporal Gap in Multimodal LLMs: Deeply Stacking Temporal Tokens for Audio-Visual Speech Recognition. | Liyong Wang, Junliang Xing, Tianyu Hu, Jianfei Jiang, Jihuai Zhao, Huimin Ma |
| 2026 | ASPDAC | Viper: An ILP-Based Vectorization Framework for Fully Homomorphic Encryption. | Weidong Yang, Xinmo Li, Xiangmin Guo, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng |
| 2025 | AAAI | RRT-MVS: Recurrent Regularization Transformer for Multi-View Stereo. | Jianfei Jiang, Liyong Wang, Haochen Yu, Tianyu Hu, Jiansheng Chen, Huimin Ma |
| 2025 | ASPDAC | MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing. | Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2025 | DAC | AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory. | Liyan Chen, Dongxu Lyu, Zhenyu Li, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2025 | DAC | KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference. | Zhenyu Li, Dongxu Lyu, Gang Wang, Yuzhou Chen, Liyan Chen, Wenjie Li, Jianfei Jiang, Yanan Sun, Guanghui He |
| 2025 | DAC | BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning. | Gang Wang, Siqi Cai, Zhenyu Li, Wenjie Li, Dongxu Lyu, Yanan Sun, Jianfei Jiang, Guanghui He |
| 2025 | DAC | VEDA: Efficient LLM Generation Through Voting-based KV Cache Eviction and Dataflow-flexible Accelerator. | Zhican Wang, Hongxiang Fan, Haroon Waris, Gang Wang, Zhenyu Li, Jianfei Jiang, Yanan Sun, Guanghui He |
| 2025 | DAC | Principle-based Dataflow Optimization for Communication Lower Bound in Operator-Fused Tensor Accelerator. | Lei Xu, Chen Yin, Zelong Yuan, Weiguang Sheng, Jianfei Jiang, Qin Wang, Naifeng Jing |
| 2025 | DATE | HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. | Weidong Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng |
| 2025 | HPCA | AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing. | Liyan Chen, Dongxu Lyu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2025 | ICCD | RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-V. | Wanqi Chen, Weidong Yang, Yiming Guo, Jing Qiu, Renpei Wang, Jianfei Jiang, Naifeng Jing, Qin Wang |
| 2025 | ICCV | MonoMVSNet: Monocular Priors Guided Multi-View Stereo Network. | Jianfei Jiang, Qiankun Liu, Haochen Yu, Hongyuan Liu, Liyong Wang, Jiansheng Chen, Huimin Ma |
| 2024 | ASPDAC | Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture. | Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2024 | ASPDAC | SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration. | Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2024 | DAC | Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators. | Lei Xu, Zhiwen Mo, Qin Wang, Jianfei Jiang, Naifeng Jing |
| 2024 | DATE | Compact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural Networks. | Xinkuang Geng, Siting Liu, Jianfei Jiang, Kai Jiang, Honglan Jiang |
| 2024 | ICASSP | DI-MVS: Learning Efficient Multi-View Stereo With Depth-Aware Iterations. | Jianfei Jiang, Mingwei Cao, Jun Yi, Chenglong Li |
| 2024 | ISCAS | A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction. | Lin Xie, Zizheng Dong, Jialei Sun, Sai Gao, Shuaipeng Li, Naifeng Jing, Qin Wang, Jianfei Jiang |
| 2023 | ASPDAC | An Efficient near-Bank Processing Architecture for Personalized Recommendation System. | Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng |
| 2023 | FPL | Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. | Pengyu Liu, Zihan Zhang, Chen Yin, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2023 | ICCD | ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. | Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Weiguang Sheng, Ang Li, Qin Wang |
| 2022 | ASPDAC | Boosting ReRAM-based DNN by Row Activation Oversubscription. | Mengyu Guo, Zihan Zhang, Jianfei Jiang, Qin Wang, Naifeng Jing |
| 2021 | DATE | Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. | Yuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng |
| 2021 | DATE | Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. | Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing |
| 2021 | ISCAS | Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator. | Yongquan Shi, Yongshuai Sun, Jianfei Jiang, Guanghui He, Qin Wang, Naifeng Jing |
| 2020 | ACCV | Frequency Attention Network: Blind Noise Removal for Real Images. | Hongcheng Mo, Jianfei Jiang, Qin Wang, Dong Yin, Pengyu Dong, Jingjun Tian |
| 2020 | ISCAS | Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array. | Tu Hong, Ning Guan, Chen Yin, Qin Wang, Jianfei Jiang, Jing Jin, Guanghui He, Naifeng Jing |
| 2019 | ISCAS | A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. | Sijie Zheng, Hongjun You, Guanghui He, Qin Wang, Tao Si, Jianfei Jiang, Jing Jin, Naifeng Jing |
| 2017 | ISCAS | A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency. | Xuwei Jin, Wei Jin, Hao Zhang, Jianfei Jiang, Weifeng He |
| 2015 | ICCAD | Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. | Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao |
| 2013 | ISCAS | Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling. | Zhenyang Chen, Qin Wang, Jing Xie, Jin Tian, Jianfei Jiang, Yufei Li, Wen Yin |
| 2012 | ISCAS | A pre-emphasis circuit design for high speed on-chip global interconnect. | Jianfei Jiang, Wei-Guang Sheng, Zhi-Gang Mao, Wei-Feng He |
| 2004 | ISCAS | Analysis of analog to digital converter based on single-electron tunnelling transistors. | Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang |