Jianfeng Luo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
4
Active years
2005–2007
Best venue rank
A*
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2007 | ASPDAC | Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process. | Subarna Sinha, Jianfeng Luo, Charles C. Chiang |
| 2007 | VLSID | Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. | Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou |
| 2006 | DAC | An IC manufacturing yield model considering intra-die variations. | Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles C. Chiang |
| 2005 | ICCAD | A layout dependent full-chip copper electroplating topography model. | Jianfeng Luo, Qing Su, Charles C. Chiang, Jamil Kawa |