Jianyi Cheng
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
25
Venues
11
Active years
2019–2026
Best venue rank
A*
Where they publish
Papers
25 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | CAV | Massively Parallel Mining of Specifications for Hardware Designs. | Leiqi Ye, Guy Frankel, Jianyi Cheng, Elizabeth Polgreen |
| 2026 | HPCA | BitDecoding: Unlocking Tensor Cores for Long-Context LLMs with Low-Bit KV Cache. | Dayou Du, Shijie Cao, Jianyi Cheng, Luo Mai, Ting Cao, Mao Yang |
| 2026 | ISCA | Combating the Memory Walls: Optimization Pathways for Long-Context Agentic Llm Inference. | Haoran Wu, Can Xiao, Jiayi Nie, Xuan Guo, Binglei Lou, Jeffrey T. H. Wong, Zhiwen Mo, Cheng Zhang, Przemyslaw Forys, Chengyang Ai, Timi Adeniran, Wayne Luk, Hongxiang Fan, Jianyi Cheng, Timothy M. Jones, Rika Antonova, Robert Mullins, Aaron Zhao |
| 2025 | ACL | Refining Salience-Aware Sparse Fine-Tuning Strategies for Language Models. | Xinxin Liu, Aaron Thomas, Cheng Zhang, Jianyi Cheng, Yiren Zhao, Xitong Gao |
| 2025 | FCCM | Microscaling Vision Transformers on FPGAs. | Can Xiao, Jianyi Cheng, Aaron Zhao |
| 2025 | FCCM | LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation. | Zixi Zhang, Balint Szekely, Pedro Gimenes, Greg Chadwick, Hugo McNally, Jianyi Cheng, Robert Mullins, Yiren Zhao |
| 2025 | FMCAD | Unlocking Hardware Verification with Oracle Guided Synthesis. | Leiqi Ye, Yixuan Li, Guy Frankel, Jianyi Cheng, Elizabeth Polgreen |
| 2025 | FPGA | Latency Insensitivity Testing for Dataflow HLS Designs. | Jianyi Cheng, Lianghui Wang, Zijian Jiang, Yungang Bao, Kan Shi |
| 2025 | FPL | Refining Datapath for Microscaling ViTs. | Can Xiao, Jianyi Cheng, Yiren Zhao |
| 2025 | ISCA | Adaptive CHERI Compartmentalization for Heterogeneous Accelerators. | Jianyi Cheng, A. Theodore Markettos, Alexandre Joannou, Paul Metzger, Matthew Naylor, Peter Rugg, Timothy M. Jones |
| 2024 | ASPLOS | SEER: Super-Optimization Explorer for High-Level Synthesis using E-graph Rewriting. | Jianyi Cheng, Samuel Coward, Lorenzo Chelini, Rafael Barbalho, Theo Drane |
| 2024 | FPL | HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator. | Zhewen Yu, Sudarshan Sreeram, Krish Agrawal, Junyi Wu, Alexander Montgomerie-Corcoran, Cheng Zhang, Jianyi Cheng, Christos-Savvas Bouganis, Yiren Zhao |
| 2024 | ICML | LQER: Low-Rank Quantization Error Reconstruction for LLMs. | Cheng Zhang, Jianyi Cheng, George Anthony Constantinides, Yiren Zhao |
| 2023 | EMNLP | Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? | Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao |
| 2023 | FPL | PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration. | Alexander Montgomerie-Corcoran, Zhewen Yu, Jianyi Cheng, Christos-Savvas Bouganis |
| 2022 | FCCM | Dynamic C-Slow Pipelining for HLS. | Jianyi Cheng, John Wickerson, George A. Constantinides |
| 2022 | FPGA | Finding and Finessing Static Islands in Dynamically Scheduled Circuits. | Jianyi Cheng, John Wickerson, George A. Constantinides |
| 2022 | FPL | Dynamic Inter-Block Scheduling for HLS. | Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson |
| 2022 | FPL | POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. | Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides |
| 2022 | HPCA | ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation. | Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, Deming Chen |
| 2021 | FCCM | Probabilistic Scheduling in High-Level Synthesis. | Jianyi Cheng, John Wickerson, George A. Constantinides |
| 2021 | FPGA | Probabilistic Optimization for High-Level Synthesis. | Jianyi Cheng, John Wickerson, George A. Constantinides |
| 2021 | FPL | Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. | Jianyi Cheng, John Wickerson, George A. Constantinides |
| 2020 | FPGA | Combining Dynamic & Static Scheduling in High-level Synthesis. | Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson |
| 2019 | FPGA | EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. | Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides |