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Jim D. Garside

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

24

Venues

12

Active years

1992–2018

Best venue rank

A*

Where they publish

Papers

24 indexed papers, newest first.

YearVenueTitleAuthors
2018ARITHApproximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip.Mantas Mikaitis, David R. Lester, Delong Shang, Steve B. Furber, Gengting Liu, Jim D. Garside, Stefan Scholze, Sebastian Hppner, Andreas Dixius
2017FPLAsynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation.Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch
2017ISCASLive demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.Sebastian Hppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Prateek Joshi, Felix Neumrker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber
2017ISCASDynamic voltage and frequency scaling for neuromorphic many-core systems.Sebastian Hppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Felix Neumrker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber
2017PLDILow overhead dynamic binary translation on ARM.Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, Mikel Lujn
2017VEEHyperMAMBO-X64: Using Virtualization to Support High-Performance Transparent Binary Translation.Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, John Goodacre, Mikel Lujn
2016FCCMParallel Hardware Merge Sorter.Wei Song, Dirk Koch, Mikel Lujn, Jim D. Garside
2016HPSROn-chip order-exploiting routing table minimization for a multicast supercomputer network.Andrew Mundy, Jonathan Heathcote, Jim D. Garside
2015DATEDe-elastisation: from asynchronous dataflows to synchronous circuits.Mahdi Jelodari Mamaghani, Jim D. Garside, Doug A. Edwards
2015FCCMAccelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study.Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Lujn
2014DSDOptimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA.Mahdi Jelodari Mamaghani, Jim D. Garside, William B. Toms, Doug A. Edwards
2014ISCASAutomatic data path extraction in large-scale register-transfer level designs.Wei Song, Jim D. Garside, Doug A. Edwards
2013DSDAutomatic Controller Detection for Large Scale RTL Designs.Wei Song, Jim D. Garside
2013DSDTransient Fault Tolerant QDI Interconnects Using Redundant Check Code.Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang
2012DATEArea efficient asynchronous SDM routers using 2-stage Clos switches.Wei Song, Doug A. Edwards, Jim D. Garside, William J. Bainbridge
2005VLSIDA Quasi-Delay-Insensitive Method to Overcome Transistor Variation.Charlie Brej, Jim D. Garside
2002DSDAn Asynchronous Victim Cache.Daranee Hormdee, Jim D. Garside, Stephen B. Furber
2002ICCDAdaptive Pipeline Depth Control for Processor Power-Management.Aristides Efthymiou, Jim D. Garside
2002ISLPEDAn adaptive serial-parallel CAM architecture for low-power cache blocks.Aristides Efthymiou, Jim D. Garside
2002VLSIDLogic Design of Asynchronous Circuits (Tutorial Abstract).Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside
2000ICCDAMULET3: A 100 MIPS Asynchronous Embedded Processor.Stephen B. Furber, David A. Edwards, Jim D. Garside
1998ICCDAMULET3: a high-performance self-timed ARM microprocessor.Stephen B. Furber, Jim D. Garside, D. A. Gilbert
1994ICCDThe Design and Evaluation of an Asynchronous Microprocessor.Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, Steve Temple, John V. Woods
1992ICCDRegister Locking in an Asynchronous Microprocessor.N. C. Paver, Paul Day, Stephen B. Furber, Jim D. Garside, John V. Woods