| 2022 | ASPDAC | A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. | Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang |
| 2020 | ISCAS | A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods. | Jinn-Shyan Wang, Cheng-Xin Xue, Chien-Tung Liu, Tay-Jyi Lin |
| 2016 | ASPDAC | Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction. | Shang-Yi Li, Pei-Yuan Chou, Jinn-Shyan Wang |
| 2011 | ASPDAC | A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. | Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng |
| 2010 | ISCAS | A 55nm 1GHz one-cycle-locking de-skewing circuit. | Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang |
| 2009 | ASPDAC | A dynamic quality-scalable H.264 video encoder chip. | Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang |
| 2009 | DAC | No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. | Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang |
| 2009 | ISCAS | A Dynamic Quality-scalable H.264 Video Encoder. | Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo |
| 2008 | ISCAS | A low-voltage latch-adder based tree multiplier. | Tzu-Yuan Kuo, Jinn-Shyan Wang |
| 2006 | DATE | An 830mW, 586kbps 1024-bit RSA chip design. | Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang |
| 2006 | DATE | A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. | Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang |
| 2006 | ICASSP | Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Application. | Jia-Wei Chen, Chien-Chang Lin, Jiun-In Guo, Jinn-Shyan Wang |
| 2006 | ISCAS | A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. | Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo |
| 2006 | ISCAS | Design of STR level converters for SoCs using the multi-island dual-VDD design technique. | Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu |
| 2006 | ISCAS | An improved SAR controller for DLL applications. | Jinn-Shyan Wang, Yi-Ming Wang, Chun-Yuan Cheng, Yu-Chia Liu |
| 2005 | ISCAS | An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang |
| 2005 | ISCAS | An all-digital pulsewidth control loop. | Yi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang |
| 2005 | ISCAS | A low-power high-SFDR CMOS direct digital frequency synthesizer. | Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh |
| 2005 | ISLPED | An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. | Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo |
| 2004 | ASPDAC | A reliable low-power fast skew-compensation circuit. | Yi-Ming Wang, Jinn-Shyan Wang |
| 2004 | ISCAS | A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen |
| 2004 | ISCAS | Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs. | Jinn-Shyan Wang, Shang-Jyh Shieh, Ching-Wei Yeh, Yuan-Hsun Yeh |
| 2004 | ISCAS | An all-digital 50% duty-cycle corrector. | Yi-Ming Wang, Jinn-Shyan Wang |
| 2004 | ISLPED | Low-power fixed-width array multipliers. | Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang |
| 2001 | ISCAS | A high-speed CMOS incrementer/decrementer. | Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang |
| 2001 | ISCAS | A high-efficiency CMOS charge pump circuit. | Sheng-Yeh Lai, Jinn-Shyan Wang |
| 2000 | ASPDAC | A new CMAC neural network architecture and its ASIC realization. | Yuan-Bao Hsu, Kao-Shing Hwang, Chien-Yuan Pao, Jinn-Shyan Wang |
| 2000 | ASPDAC | Power analysis and implementation of a low-power 300 MHz 8-b 8-b pipelined multiplier. | Jinn-Shyan Wang, Po-Hui Yang |
| 2000 | ICCAD | Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. | Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang |
| 2000 | ISCAS | A high-speed single-phase-clocked CMOS priority encoder. | Jinn-Shyan Wang, Chun-Shing Huang |
| 2000 | ISCAS | A compact adaptive equalizer IC for HIPERLAN system. | Jinn-Shyan Wang, Pei-Lung Lin, Wern-Ho Sheen, Duo Sheng, Yu-Ming Huang |
| 2000 | ISCAS | A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops. | Po-Hui Yang, Jinn-Shyan Wang, Yi-Ming Wang |
| 1999 | ASPDAC | Technnology Mapping for Low Power. | Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang |
| 1999 | DAC | Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs. | Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang |
| 1999 | ISCAS | A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM. | Ching-Rong Chang, Jinn-Shyan Wang |
| 1999 | ISCAS | A cell selection strategy for low power applications. | Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang |
| 1998 | ISLPED | Low-power embedded SRAM macros with current-mode read/write operations. | Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng |
| 1995 | ISCAS | Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. | Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu |