Joe D. Rutledge
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
1986–1986
Best venue rank
A
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1986 | ITC | Efficient Fault Simulation of CMOS Circuits with Accurate Models. | Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman |