Johannes Zeppenfeld
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
5
Active years
2007–2012
Best venue rank
C
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | DDECS | A low-overhead monitoring ring interconnect for MPSoC parameter optimization. | Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf |
| 2011 | DDECS | An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. | Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf |
| 2010 | DATE | A rapid prototyping system for error-resilient multi-processor systems-on-chip. | Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jrgen Teich |
| 2010 | ISORC | Towards Scalability and Reliability of Autonomic Systems on Chip. | Johannes Zeppenfeld, Abdelmajid Bouajila, Andreas Herkersdorf, Walter Stechele |
| 2008 | GI | Learning Classifier Tables for Autonomic Systems on Chip. | Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf |
| 2007 | DATE | Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. | Christopher Claus, Johannes Zeppenfeld, Florian Helmut Mller, Walter Stechele |
| 2007 | DSD | Power Estimation of Time Variant SoCs with TAPES. | Andreas Lankes, Thomas Wild, Johannes Zeppenfeld |