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Jon Prez

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

20

Venues

8

Active years

2009–2023

Best venue rank

C

Where they publish

Papers

20 indexed papers, newest first.

YearVenueTitleAuthors
2023DATESAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AI.Jaume Abella, Jon Prez, Cristofer Englund, Bahram Zonooz, Gabriele Giordana, Carlo Donzella, Francisco J. Cazorla, Enrico Mezzetti, Isabel Serra, Axel Brando, Irune Agirre, Fernando Eizaguirre, Thanh Hai Bui, Elahe Arani, Fahad Sarfraz, Ajay Balasubramaniam, Ahmed Badar, Ilaria Bloise, Lorenzo Feruglio, Ilaria Cinelli, Davide Brighenti, Davide Cunial
2021DATEEstimation of Linux Kernel Execution Path Uncertainty for Safety Software Test Coverage.Imanol Allende, Nicholas Mc Guire, Jon Prez, Lisandro Gabriel Monsalve, Javier Fernndez, Roman Obermaisser
2019EDCCTowards Linux for the Development of Mixed-Criticality Embedded Systems Based on Multi-Core Devices.Imanol Allende, Nicholas Mc Guire, Jon Prez, Lisandro Gabriel Monsalve, Nerea Uriarte, Roman Obermaisser
2017DSDModular Development and Certification of Dependable Mixed-Criticality Systems.Asier Larrucea, Imanol Martinez, Carlos Fernando Nicols, Jon Prez, Roman Obermaisser
2017SAFECOMPGSN Support of Mixed-Criticality Systems Certification.Carlos Fernando Nicols, Fernando Eizaguirre, Asier Larrucea, Simon Barner, Franck Chauvel, Goiuria Sagardui, Jon Prez
2016DSDA Realistic Approach to a Network-on-Chip Cross-Domain Pattern.Asier Larrucea, Hamidreza Ahmadian, Roman Obermaisser, Jon Prez, Carlos Fernando Nicols
2016DSDSAFEPOWER Project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems.Alina Lenz, Mikel Azkarate-Askasua Blazquez, Javier Coronel, Alfons Crespo, Simon Davidmann, Juan Carlos Diaz Garcia, Nera Gonzlez Romero, Kim Grttner, Roman Obermaisser, Johnny berg, Jon Prez, Ingo Sander, Ingemar Sderquist
2016SAFECOMPAutomotive Safety Concept Definition for Mixed-Criticality Integration on a COTS Multicore.Irune Agirre, Mikel Azkarate-askasua, Asier Larrucea, Jon Prez, Tullio Vardanega, Francisco J. Cazorla
2015DSDIEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis.Irune Agirre, Mikel Azkarate-askasua, Carles Hernndez, Jaume Abella, Jon Prez, Tullio Vardanega, Francisco J. Cazorla
2015DSDA Modular Safety Case for an IEC-61508 Compliant Generic Hypervisor.Asier Larrucea, Jon Prez, Irune Agirre, Vicent Brocal, Roman Obermaisser
2015FDLTemporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioning.Asier Larrucea, Irune Agirre, Carlos Fernando Nicols, Jon Prez, Mikel Azkarate-askasua, Ton Trapman
2014DSDA Safety Certification Strategy for IEC-61508 Compliant Industrial Mixed-Criticality Systems Based on Multicore Partitioning.Jon Prez, David Gonzlez, Carlos Fernando Nicols, Ton Trapman, Jose Miguel Garate
2014FDLA novel modeling framework for time-triggered safety-critical embedded systems.Iban Ayestaran, Carlos Fernando Nicols, Jon Prez, Asier Larrucea, Peter P. Puschner
2014ISORCModeling and Simulated Fault Injection for Time-Triggered Safety-Critical Embedded Systems.Iban Ayestaran, Carlos Fernando Nicols, Jon Prez, Asier Larrucea, Peter P. Puschner
2014SAFECOMPA Simulated Fault Injection Framework for Time-Triggered Safety-Critical Embedded Systems.Iban Ayestaran, Carlos Fernando Nicols, Jon Prez, Asier Larrucea, Peter P. Puschner
2013ETFASCA extensions to support safety critical distributed embedded systems.Aitor Agirre, Jon Prez, Rafael Priego, Marga Marcos, Elisabet Estvez-Estvez
2010EDCCCodesign and Simulated Fault Injection of Safety-Critical Embedded Systems Using SystemC.Jon Prez, Mikel Azkarate-askasua, Antonio Perez
2010FDLModeling Time-Triggered Architecture Based Safety-Critical Embedded Systems Using SystemC.Jon Prez, Carlos Fernando Nicols, Roman Obermaisser, Christian El Salloum
2010ISORCExecutable Time-Triggered Model (E-TTM) for Real-Time Control Systems.Jon Prez, Antonio Perez, Roman Obermaisser
2009FPLA novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs.Xabier Iturbe, Mikel Azkarate-askasua, Imanol Martinez, Jon Prez, Armando Astarloa