Jorge Juan-Chico
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2000–2001
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2001 | DATE | HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. | Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero |
| 2001 | ISCAS | Gate-level simulation of CMOS circuits using the IDDM model. | Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero |
| 2000 | ISCAS | Inertial and degradation delay model for CMOS logic gates. | Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia |