Jos-Alejandro Lpez Alcantud
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
4
Active years
2000–2017
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | ISCAS | An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. | Jos ngel Daz-Madrid, Gins Domnech-Asensi, Jos-Alejandro Lpez Alcantud, M. Oberst |
| 2006 | FPL | Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. | Gins Domnech-Asensi, Juan Martnez-Alajarn, Ramn Ruiz Merino, Jos-Alejandro Lpez Alcantud |
| 2005 | IWINAC | Description and Simulation of Bio-inspired Systems Using VHDL-AMS. | Gins Domnech-Asensi, Jos-Alejandro Lpez Alcantud, Ramn Ruiz Merino |
| 2003 | IWANN | An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks. | Jos-Alejandro Lpez Alcantud, Jos ngel Daz-Madrid, Hans Hauer, Ramn Ruiz Merino |
| 2000 | ISCAS | VHDL-AMS modeling of self-organizing neural systems. | Jos-Alejandro Lpez Alcantud, Tom Kazmierski |