Jos Manuel Cazeaux
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2004–2006
Best venue rank
C
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | DATE | Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. | Martin Omaa, Jos Manuel Cazeaux, Daniele Rossi, Cecilia Metra |
| 2006 | DDECS | Can Clock Faults be Detected Through Functional Test? | Cecilia Metra, Daniele Rossi, Martin Omaa, Jos Manuel Cazeaux, T. M. Mak |
| 2006 | IOLTS | Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. | Cecilia Metra, Martin Omaa, Daniele Rossi, Jos Manuel Cazeaux, T. M. Mak |
| 2005 | IOLTS | On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. | Jos Manuel Cazeaux, Daniele Rossi, Martin Omaa, Cecilia Metra, Abhijit Chatterjee |
| 2004 | IOLTS | Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. | Jos Manuel Cazeaux, Martin Omaa, Cecilia Metra |
| 2004 | IOLTS | New High Speed CMOS Self-Checking Voter. | Jos Manuel Cazeaux, Daniele Rossi, Cecilia Metra |