| 2025 | ISCAS | Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs. | Gins Domnech-Asensi, Francisco Javier Andreo-Oliver, Ramn Ruiz Merino, Jos ngel Daz-Madrid |
| 2023 | ISCAS | A 12T SRAM in-Memory Computing differential current architecture for CNN implementations. | Gins Domnech-Asensi, Ramn Ruiz Merino, Juan Zapata-Prez, Jos ngel Daz-Madrid |
| 2020 | ISCAS | Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. | Jos ngel Daz-Madrid, Gins Domnech-Asensi, Ramn Ruiz Merino, Juan Zapata-Prez, Jos Javier Martnez |
| 2017 | ISCAS | An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. | Jos ngel Daz-Madrid, Gins Domnech-Asensi, Jos-Alejandro Lpez Alcantud, M. Oberst |
| 2009 | DATE | Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. | Jos ngel Daz-Madrid, Harald Neubauer, Hans Hauer, Gins Domnech-Asensi, Ramn Ruiz Merino |
| 2008 | ISCAS | Accurate and reusable macromodeling technique using a fuzzy-logic approach. | Gins Domnech-Asensi, Juan Hinojosa, Ramn Ruiz Merino, Jos ngel Daz-Madrid |
| 2007 | IWINAC | Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits. | Jos ngel Daz-Madrid, Pedro Monsalve-Campillo, Juan Hinojosa, Mara Victoria Rodellar Biarge, Gins Domnech-Asensi |
| 2003 | IWANN | An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks. | Jos-Alejandro Lpez Alcantud, Jos ngel Daz-Madrid, Hans Hauer, Ramn Ruiz Merino |
| 2003 | IWANN | Current Mode CMOS Synthesis of a Motor-Control Neural System. | Gins Domnech-Asensi, Ramn Ruiz Merino, Hans Hauer, Jos ngel Daz-Madrid |