| 2026 | ISPASS | HOTP - High-conf Only Taken Predictor for Efficient Superscalar Multi-level Branch Predictor. | Bhawandeep Singh Harsh, Jose Renau |
| 2023 | CC | A Multi-threaded Fast Hardware Compiler for HDLs. | Sheng-Hong Wang, Hunter James Coffman, Kenneth Mayer, Sakshi Garg, Jose Renau |
| 2021 | MICRO | Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation. | Nursultan Kabylkas, Tommy Thorn, Shreesha Srinath, Polychronis Xekalakis, Jose Renau |
| 2020 | ISPASS | LiveSim: A Fast Hot Reload Simulator for HDLs. | Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau |
| 2019 | DAC | SMatch: Structural Matching for Fast Resynthesis in FPGAs. | Rafael Trapani Possignolo, Jose Renau |
| 2019 | MICRO | EMI Architectural Model and Core Hopping. | Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau |
| 2017 | DAC | LiveSynth: Towards an Interactive Synthesis Flow. | Rafael Trapani Possignolo, Jose Renau |
| 2017 | ISCAS | Timing speculative SRAM. | Elnaz Ebrahimi, Matthew R. Guthaus, Jose Renau |
| 2017 | ISCAS | Level shifter design for voltage stacking. | Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau |
| 2017 | MEMOCODE | Liam: an actor based programming model for HDLs. | Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau |
| 2017 | MICRO | Architectural opportunities for novel dynamic EMI shifting (DEMIS). | Daphne I. Gorman, Matthew R. Guthaus, Jose Renau |
| 2016 | HPCA | LiveSim: Going live with microarchitecture simulation. | Sina Hassani, Gabriel Southern, Jose Renau |
| 2016 | ICCD | Fluid Pipelines: Elastic circuitry meets Out-of-Order execution. | Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau |
| 2016 | ISCAS | SRAM voltage stacking. | Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau |
| 2016 | ISPASS | Analysis of PARSEC workload scalability. | Gabriel Southern, Jose Renau |
| 2015 | ISPASS | Message from the program chair. | Jose Renau |
| 2015 | PPoPP | Section based program analysis to reduce overhead of detecting unsynchronized thread communication. | Madan Mohan Das, Gabriel Southern, Jose Renau |
| 2013 | HPCA | ESESC: A fast multicore simulator using Time-Based Sampling. | Ehsan K. Ardestani, Jose Renau |
| 2013 | ISLPED | An energy efficient GPGPU memory hierarchy with tiny incoherent caches. | Alamelu Sankaranarayanan, Ehsan K. Ardestani, Jos Luis Briz, Jose Renau |
| 2012 | ISLPED | Thermal-aware sampling in architectural simulation. | Ehsan K. Ardestani, Elnaz Ebrahimi, Gabriel Southern, Jose Renau |
| 2011 | ISCA | Releasing efficient beta cores to market early. | Sangeetha Sudhakrishnan, Rigo Dicochea, Jose Renau |
| 2010 | ASPLOS | Characterizing processor thermal behavior. | Francisco J. Mesa-Martinez, Ehsan K. Ardestani, Jose Renau |
| 2009 | FPGA | Measuring and modeling variabilityusing low-cost FPGAs. | Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau |
| 2009 | ISLPED | SOI, interconnect, package, and mainboard thermal characterization. | Joseph Nayfach-Battilana, Jose Renau |
| 2008 | MSR | Understanding bug fix patterns in verilog. | Sangeetha Sudhakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau |
| 2007 | ISCA | Power model validation through thermal measurements. | Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau |
| 2007 | MICRO | Effective Optimistic-Checker Tandem Core Design through Architectural Pruning. | Francisco J. Mesa-Martinez, Jose Renau |
| 2006 | PPoPP | POSH: a TLS compiler that exploits program structure. | Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas |
| 2005 | ICS | Thread-Level Speculation on a CMP can be energy efficient. | Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas |
| 2005 | ICS | Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. | Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas |
| 2005 | MICRO | uComplexity: Estimating Processor Design Effort. | Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau |
| 2003 | ISCA | Positional Adaptation of Processors: Application to Energy Reduction. | Michael C. Huang, Jose Renau, Josep Torrellas |
| 2003 | PPoPP | Programming the FlexRAM parallel intelligent memory system. | Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas |
| 2002 | ISLPED | Energy-efficient hybrid wakeup logic. | Michael C. Huang, Jose Renau, Josep Torrellas |
| 2002 | MICRO | Cherry: checkpointed early resource recycling in out-of-order microprocessors. | Jos F. Martnez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas |
| 2001 | ISLPED | L1 data cache decomposition for energy efficiency. | Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas |
| 2000 | MICRO | A framework for dynamic energy efficiency and temperature management. | Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas |