| 2025 | ISCAS | A Novel Energy-Efficient Continuous-Time Hysteretic VCO-Based Comparator. | Jinhen Lee, Victor Adrian, Kinglouis Steven Tantra, Bah-Hwee Gwee, Joseph S. Chang |
| 2025 | ISCAS | Live Demonstration: AI-based System Latchup Detection and Protection for COTS Systems. | Yin Sun, Junkai Zhao, Rouli Fang, Tony Zhang, Kwen-Siong Chong, Wei Shu, Joseph S. Chang |
| 2025 | ISCAS | A Novel High-Accuracy Inductor-Current Estimator for Digitally-Controlled Synchronous DC-DC Buck Converters. | Yanshan Xie, Victor Adrian, Jinhen Lee, Joseph S. Chang |
| 2025 | ISCAS | An Adaptive AI-based Approach to Detect and Protect COTS Systems against Micro-Single-Event-Latchups (μ-SELs) and SELs. | Junkai Zhao, Yin Sun, Tony Zhang, Kwen-Siong Chong, Wei Shu, Joseph S. Chang |
| 2023 | ISCAS | A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters. | Jinhen Lee, Victor Adrian, Sun-Yang Tay, Yanshan Xie, Bah-Hwee Gwee, Joseph S. Chang |
| 2023 | ISCAS | An Accurate Digital Inductor Current Sensor for Current-Ripple-Based DC-DC Converters. | Yanshan Xie, Victor Adrian, Sun-Yang Tay, Jinhen Lee, Pak Kwong Chan, Joseph S. Chang |
| 2022 | ISCAS | An Integrated DC-DC Converter with Novel Asymmetrical Segmented Power-Stages for Sustained High Power-Efficiencies. | Jinhen Lee, Victor Adrian, Joseph S. Chang, Yin Sun, Sun-Yang Tay |
| 2022 | ISCAS | An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. | Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee |
| 2022 | ISCAS | A Versatile and Accurate Vector-Based Method for Modeling and Analyzing Planar Air-Core Inductors. | Sun-Yang Tay, Victor Adrian, Joseph S. Chang, Jinhen Lee, Bah-Hwee Gwee |
| 2020 | ISCAS | Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller. | Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Wei Shu, Joseph S. Chang |
| 2020 | ISCAS | A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. | Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
| 2019 | ISCAS | Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. | Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, Wei Shu, Joseph S. Chang, Bah-Hwee Gwee |
| 2018 | ISCAS | An Air-Core Coupled-Inductor Based Dual-Phase Output Stage for Point-of-Load Converters. | Yong Qu, Wei Shu, Joseph S. Chang |
| 2018 | ISCAS | Power-Loss and Design Space Analyses for Fully-Integrated Switched-Mode DC-DC Converters. | Yin Sun, Victor Adrian, Joseph S. Chang |
| 2018 | ISCAS | Flexible Hybrid Electronics: Review and Challenges. | Tong Ge, Zhou Jia, Joseph S. Chang |
| 2017 | ISCAS | Review: A fully-additive printed electronics process with very-low process variations (Bent and unbent substrates) and PDK. | Tong Ge, Jia Zhou, Yang Kang, Joseph S. Chang |
| 2017 | ISCAS | A class-E RF power amplifier with a novel matching network for high-efficiency dynamic load modulation. | Qianqian Liu, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang |
| 2017 | ISCAS | A novel high-rate hybrid window ADC design for monolithic digitally-controlled DC-DC converters. | Yin Sun, Victor Adrian, Joseph S. Chang |
| 2016 | ISCAS | An investigation of THD of a BTL Class D amplifier. | Tong Ge, Huiqiao He, Jia Zhou, Yang Kang, Joseph S. Chang |
| 2016 | ISCAS | Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process. | Tong Lin, Kwen-Siong Chong, Wei Shu, Ne Kyaw Zwa Lwin, Jize Jiang, Joseph S. Chang |
| 2016 | ISCAS | Fully-additive printed electronics: Process Development Kit. | Jia Zhou, Tong Ge, Joseph S. Chang |
| 2015 | ISCAS | High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). | Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang |
| 2015 | ISCAS | Design of a variable-delay window ADC for switched-mode DC-DC converters. | Yin Sun, Victor Adrian, Joseph S. Chang |
| 2015 | ISCAS | A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. | Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang |
| 2014 | ISCAS | Synthesis of asynchronous QDI circuits using synchronous coding specifications. | Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho |
| 2013 | ISCAS | A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. | Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
| 2013 | ISCAS | Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. | Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
| 2012 | ISCAS | A comparative study on asynchronous Quasi-Delay-Insensitive templates. | Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
| 2012 | ISCAS | An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. | Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
| 2012 | ISCAS | Energy-delay efficient asynchronous-logic 1616-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. | Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang |
| 2000 | ISCAS | An investigation on the parameters affecting total harmonic distortion in class D amplifiers. | Meng Tong Tan, Hock-Chuan Chua, Bah-Hwee Gwee, Joseph S. Chang |