Juan A. Prieto
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
3
Active years
1994–1998
Best venue rank
A
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1998 | DATE | An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. | Juan A. Prieto, Adoracin Rueda, Ian Andrew Grout, Eduardo J. Peralas, Jos L. Huertas, Andrew Mark David Richardson |
| 1998 | ITC | DfT and on-line test of high-performance data converters: a practical case. | Eduardo J. Peralas, Adoracin Rueda, Juan A. Prieto, Jos L. Huertas |
| 1997 | DATE | A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs. | Juan A. Prieto, Adoracin Rueda, Jos M. Quintana, Jos Luis Huertas |
| 1994 | ISCAS | An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits. | Juan A. Prieto, Jos M. Quintana, Adoracin Rueda, Jos L. Huertas |