| 2016 | IOLTS | Efficient fault tolerant parallel matrix-vector multiplications. | Zhen Gao, Pedro Reviriego, Juan Antonio Maestro |
| 2012 | IOLTS | Low Power embedded DRAM caches using BCH code partitioning. | Pedro Reviriego, Alfonso Snchez-Macin, Juan Antonio Maestro |
| 2011 | DAC | Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors. | Pedro Reviriego, Juan Antonio Maestro, Sanghyeon Baeg |
| 2011 | DDECS | Validation and optimization of TMR protections for circuits in radiation environments. | Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego |
| 2011 | Networking | Using Coordinated Transmission with Energy Efficient Ethernet. | Pedro Reviriego, Ken Christensen, Alfonso Snchez-Macin, Juan Antonio Maestro |
| 2011 | Networking | On the Impact of the TCP Acknowledgement Frequency on Energy Efficient Ethernet Performance. | Pedro Reviriego, Alfonso Snchez-Macin, Juan Antonio Maestro |
| 2009 | IOLTS | Soft error detection and correction for FFT based convolution using different block lengths. | Pedro Reviriego, Juan Antonio Maestro, Anne O'Donnell, Chris J. Bleakley |
| 2008 | DAC | Study of the effects of MBUs on the reliability of a 150 nm SRAM device. | Juan Antonio Maestro, Pedro Reviriego |
| 2007 | DDECS | An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. | Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego |
| 1999 | DATE | The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. | Juan Antonio Maestro, Daniel Mozos, Romn Hermida |
| 1998 | DATE | A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process. | Juan Antonio Maestro, Daniel Mozos, Hortensia Mecha |