Judit Freijedo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2007–2013
Best venue rank
C
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | FPL | Aging monitoring with local sensors in FPGA-based designs. | Carlos Leong, Jorge Semio, Isabel C. Teixeira, Marcelino B. Santos, Joo Paulo Teixeira, Mara Dolores Valds, Judit Freijedo, Juan J. Rodrguez-Andina, Fabian Vargas |
| 2011 | FPL | Performance Failure Prediction Using Built-In Delay Sensors in FPGAs. | Vasco Bexiga, Carlos Leong, Jorge Semio, Isabel C. Teixeira, Joo Paulo Teixeira, Mara Dolores Valds, Judit Freijedo, Juan J. Rodrguez-Andina, Fabian Vargas |
| 2009 | IOLTS | Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies. | Jorge Semio, Judit Freijedo, Juan J. Rodrguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, Joo Paulo Teixeira |
| 2008 | IOLTS | Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits. | Jorge Semio, Judit Freijedo, Juan J. Rodrguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, Joo Paulo Teixeira |
| 2007 | DDECS | Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. | Jorge Semio, Judit Freijedo, Juan J. Rodrguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, Joo Paulo Teixeira |
| 2007 | IOLTS | On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. | Jorge Semio, Judit Freijedo, Juan J. Rodrguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, Joo Paulo Teixeira |