| 2019 | ASPDAC | Path controllability analysis for high quality designs. | Li-Jie Chen, Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo, Chi-Lai Huang |
| 2015 | DAC | Scalable sequence-constrained retention register minimization in power gating design. | Ting-Wei Chiang, Kai-Hui Chang, Yen-Ting Liu, Jie-Hong R. Jiang |
| 2012 | DAC | Improving gate-level simulation accuracy when unknowns exist. | Kai-Hui Chang, Chris Browy |
| 2012 | DATE | RTL analysis and modifications for improving at-speed test. | Kai-Hui Chang, Hong-Zu Chou, Igor L. Markov |
| 2012 | MEMOCODE | Improving design verifiability by early RTL coverability analysis. | Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu |
| 2011 | ASPDAC | Facilitating unreachable code diagnosis and debugging. | Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo |
| 2011 | DATE | Formal reset recovery slack calculation at the register transfer level. | Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo |
| 2011 | ICCD | Applying verification intention for design customization via property mining under constrained testbenches. | Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo |
| 2010 | ASPDAC | Optimizing blocks in an SoC using symbolic code-statement reachability analysis. | Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo |
| 2010 | DATE | Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study. | Hong-Zu Chou, Haiqian Yu, Kai-Hui Chang, Dylan Dobbyn, Sy-Yen Kuo |
| 2009 | DAC | Handling don't-care conditions in high-level synthesis and application for reducing initialized registers. | Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo |
| 2009 | DATE | Customizing IP cores for system-on-chip designs using extensive external don't-cares. | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov |
| 2007 | ASPDAC | Safe Delay Optimization for Physical Synthesis. | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
| 2007 | ASPDAC | Fixing Design Errors with Counterexamples and Resynthesis. | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
| 2007 | ASPDAC | Node Mergers in the Presence of Don't Cares. | Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
| 2007 | ICCAD | Automating post-silicon debugging and repair. | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
| 2005 | FORTE | Automatic Partitioner for Behavior Level Distributed Logic Simulation. | Kai-Hui Chang, Jeh-Yen Kang, Han-Wei Wang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo |
| 2005 | ICCAD | Simulation-based bug trace minimization with BMC-based refinement. | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov |
| 2005 | ICCAD | Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
| 2004 | ATVA | A Temporal Assertion Extension to Verilog. | Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo |