Kattekola Naresh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2022–2022
Best venue rank
National
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | VLSID | Design of 8-bit Dadda Multiplier using Gate Level Approximate 4: 2 Compressor. | Kattekola Naresh, Y. Padma Sai, Shubhankar Majumdar |