Design of 8-bit Dadda Multiplier using Gate Level Approximate 4: 2 Compressor.
Kattekola Naresh, Y. Padma Sai, Shubhankar Majumdar
Browse the full VLSID paper archive.
Kattekola Naresh, Y. Padma Sai, Shubhankar Majumdar
Browse the full VLSID paper archive.