Shubhankar Majumdar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2022–2026
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DDECS | A Model-Driven Approach to Variable-Frequency Clock Synthesis for PSN-Resilient IC Wake-Up. | Vipin Kumar Singh, Vijay Pratap Yadav, Vassilis Alimisis, Paul P. Sotiriadis, Shubhankar Majumdar, Alak Majumder |
| 2022 | VLSID | Design of 8-bit Dadda Multiplier using Gate Level Approximate 4: 2 Compressor. | Kattekola Naresh, Y. Padma Sai, Shubhankar Majumdar |