Kaushik Narayanun
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
3
Active years
2016–2024
Best venue rank
National
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | ITC | A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS. | Kunal Jain Mangilal, Mahmut Yilmaz, Vishal Agarwal, Shantanu Sarangi, Kaushik Narayanun |
| 2022 | ICCAD | Observation Point Insertion Using Deep Learning. | Bonita Bhaskaran, Sanmitra Banerjee, Kaushik Narayanun, Shao-Chun Hung, Seyed Nima Mozaffari Mojaveri, Mengyun Liu, Gang Chen, Tung-Che Liang |
| 2022 | VTS | NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. | Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey |
| 2019 | ITC | An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test. | Seyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn |
| 2017 | VTS | Test-cost optimization in a scan-compression architecture using support-vector regression. | Zipeng Li, Jonathon E. Colburn, Vinod Pagalone, Kaushik Narayanun, Krishnendu Chakrabarty |
| 2016 | VTS | Test method and scheme for low-power validation in modern SOC integrated circuits. | Bonita Bhaskaran, Amit Sanghani, Kaushik Narayanun, Ayub Abdollahian, Amit Laknaur |
| 2016 | VTS | A programmable method for low-power scan shift in SoC integrated circuits. | Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani |