| 2000 | ASPDAC | A method for linking process-level variability to system performances. | Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru |
| 1999 | DAC | A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru |
| 1998 | ICASSP | A new architecture for in-memory image convolution. | Vasily G. Moshnyaga, Kazuhiro Suzuki, Keikichi Tamaru |
| 1998 | ICASSP | Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization. | Kazuhiko Terada, Masahiro Takeuchi, Kazutoshi Kobayashi, Keikichi Tamaru |
| 1998 | ICCAD | Proposal of a timing model for CMOS logic gates driving a CRC load. | Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru |
| 1998 | ISLPED | A power optimization method considering glitch reduction by gate sizing. | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru |
| 1997 | ASPDAC | A functional memory type parallel processor for vector quantization. | Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru |
| 1997 | ASPDAC | A current mode cyclic A/D converter with a 0.8 μm CMOS process. | Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru |
| 1997 | ICASSP | A memory efficient array architecture for full-search block matching algorithm. | Vasily G. Moshnyaga, Keikichi Tamaru |
| 1995 | ASPDAC | A model-adaptable MOSFET parameter extraction system. | Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru |
| 1995 | ASPDAC | A scheduling algorithm for synthesis of bus-partitioned architectures. | Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru |
| 1995 | ICCAD | An iterative gate sizing approach with accurate delay evaluation. | Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru |
| 1995 | ISCAS | A New Algorithm for Sorting Problem with Reformed CAM. | Kuei-Ming Lu, Keikichi Tamaru |
| 1995 | ISCAS | A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. | Vasily G. Moshnyaga, Keikichi Tamaru |
| 1993 | ICASSP | High speed merged multiplication. | Farhad Fuad Islam, Keikichi Tamaru |
| 1993 | ICCAD | Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. | Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru |
| 1993 | ISCAS | An Architecture for Intermediate Area-time Complexity Multiplier. | Farhad Fuad Islam, Keikichi Tamaru |
| 1991 | DAC | Branch-and-Bound Placement for Building Block Layout. | Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru |
| 1990 | ICCAD | Extraction of Functional Information from Combinatorial Circuits. | M. Ohmura, Hiroto Yasuura, Keikichi Tamaru |