| 2011 | ASPDAC | Biological information sensing technologies for medical, health care, and wellness applications. | Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato |
| 2010 | ISCAS | Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm. | Hassan A. Youness, Abdel-Moniem Wahdan, Mohammed Hassan, Ashraf Salem, Mohammed Moness, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2009 | ASPDAC | Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. | Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2007 | ASPDAC | A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. | Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2007 | ICASSP | A Block-Floating-Point Processor for Rapid Application Development. | Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Shiro Kobayashi |
| 2005 | ASPDAC | Enabling RTOS simulation modeling in a system level design language. | M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2005 | DATE | RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. | M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2004 | ASPDAC | Synthesizable HDL generation method for configurable VLIW processors. | Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2004 | DATE | Architecture-Level Performance Estimation for IP-Based Embedded Systems. | Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2004 | ISCAS | S-sequence: a new floorplan representation method preserving room abutment relationships. | Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai |
| 2003 | ASPDAC | An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost. | Changwen Zhuang, Keishi Sakanushi, Liyan Jin, Yoji Kajitani |
| 2003 | SCOPES | A Code Selection Method for SIMD Processors with PACK Instructions. | Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai |
| 2002 | DATE | An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. | Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin |
| 1998 | ICCAD | The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. | Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita |
| 1998 | ICCAD | The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. | Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani |