Kenichi Okada
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
50
Venues
6
Active years
2000–2025
Best venue rank
B
Where they publish
Papers
50 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPDAC | A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO. | Chenxin Liu, Zheng Li, Yudai Yamazaki, Hans Herdian, Chun Wang, Anyi Tian, Jun Sakamaki, Han Nie, Xi Fu, Sena Kato, Wenqian Wang, Hongye Huang, Shinsuke Hara, Akifumi Kasamatsu, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada |
| 2025 | ASPDAC | A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25-71GHz for Multi-Band 5G NR. | Dongfan Xu, Minzhe Tang, Yi Zhang, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada |
| 2025 | ASPDAC | A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data Rate. | Yi Zhang, Minzhe Tang, Zheng Li, Dongfan Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada |
| 2024 | ISCAS | Sub-THz CMOS Phased-Array Transceiver Design for 6G. | Kenichi Okada |
| 2024 | ISCAS | A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases. | Sidharth Thomas, Jaskirat Singh Virdi, Anshul Verma, Bishnu Prasad Das, Kenichi Okada, Pratap Narayan Singh |
| 2024 | ISCAS | A 24-71-GHz Tri-Mode Mixer Using Harmonic Selection for Multi-Band 5G NR. | Dongfan Xu, Minzhe Tang, Yi Zhang, Zheng Li, Atsushi Shirane, Kenichi Okada |
| 2022 | PIMRC | Millimeter-Wave CMOS Phased-Array Transceivers for 5G and Beyond. | Kenichi Okada, Jian Pang, Atsushi Shirane, Zheng Li, Yi Zhang, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro |
| 2021 | ASPDAC | A 0.41W 34Gb/s 300GHz CMOS Wireless Transceiver. | Ibrahim Abdo, Takuya Fujimura, Tsuyoshi Miura, Korkut Kaan Tokgoz, Atsushi Shirane, Kenichi Okada |
| 2021 | ASPDAC | A High Accuracy Phase and Amplitude Detection Circuit for Calibration of 28GHz Phased Array Beamformer System. | Joshua Alvin, Jian Pang, Atsushi Shirane, Kenichi Okada |
| 2021 | ASPDAC | A DSM-based Polar Transmitter with 23.8% System Efficiency. | Yuncheng Zhang, Bangan Liu, Xiaofan Gu, Chun Wang, Atsushi Shirane, Kenichi Okada |
| 2021 | ASPDAC | 28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver. | Yi Zhang, Jian Pang, Kiyoshi Yanagizawa, Atsushi Shirane, Kenichi Okada |
| 2020 | ASPDAC | A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR. | Zheng Li, Jian Pang, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Joshua Alvin, Bangan Liu, Zheng Sun, Hongye Huang, Atsushi Shirane, Kenichi Okada |
| 2019 | ISCAS | Millimeter-Wave CMOS Transceiver Toward 1Tbps Wireless Communication. | Korkut Kaan Tokgoz, Kenichi Okada |
| 2017 | ASPDAC | W-band ultra-high data-rate 65nm CMOS wireless transceiver. | Korkut Kaan Tokgoz, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa |
| 2017 | ASPDAC | An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. | Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa |
| 2016 | ASPDAC | A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. | Aravind Tharayil Narayanan, Makihiko Katsuragi, Kengo Nakata, Yuki Terashima, Kenichi Okada, Akira Matsuzawa |
| 2016 | ASPDAC | An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. | Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa |
| 2015 | ASPDAC | A tail-current modulated VCO with adaptive-bias scheme. | Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa |
| 2015 | ASPDAC | A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. | Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa |
| 2015 | ASPDAC | An HDL-synthesized gated-edge-injection PLL with a current output DAC. | Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa |
| 2014 | ASPDAC | A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. | Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa |
| 2014 | ASPDAC | A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. | Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa |
| 2013 | ASPDAC | A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios. | Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa |
| 2013 | ASPDAC | A full 4-channel 60 GHz direct-conversion transceiver. | Seitaro Kawai, Ryo Minami, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Yuki Tsukui, Kenichi Okada, Akira Matsuzawa |
| 2013 | ASPDAC | A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. | Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa |
| 2012 | AINA | ADEC: Assured Deletion and Verifiable Version Control for Cloud Storage. | Shin Tezuka, Ryuya Uda, Kenichi Okada |
| 2012 | ASPDAC | A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique. | Wei Deng, Kenichi Okada, Akira Matsuzawa |
| 2012 | ASPDAC | A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS. | Ryo Minami, Hiroki Asada, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Win Chaivipas, Kenichi Okada, Akira Matsuzawa |
| 2012 | ASPDAC | A Progressive Mixing 20GHz ILFD with wide locking range for higher division ratios. | Ahmed Musa, Kenichi Okada, Akira Matsuzawa |
| 2011 | ASPDAC | An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation. | Wei Deng, Kenichi Okada, Akira Matsuzawa |
| 2011 | ASPDAC | A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique. | Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa |
| 2010 | AINA | Development of Hi-Speed X.509 Certification Path Validation System. | Takahiro Fujishiro, Akane Sato, Yoko Kumagai, Tadashi Kaji, Kenichi Okada |
| 2010 | ASPDAC | A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters. | Daisuke Imanishi, Jee Young Hong, Kenichi Okada, Akira Matsuzawa |
| 2010 | ASPDAC | A 60GHz direct-conversion transmitter in 65nm CMOS technology. | Naoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa |
| 2009 | AINA | The Efficiency Method of Sanitizable Signature Scheme for SMF. | Hirokazu Miyata, Ryuya Uda, Kenichi Okada |
| 2009 | GECCO | The study of the knowledge optimization tool. | Akira Otsuki, Kenichi Okada |
| 2008 | ASPDAC | LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. | Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu |
| 2008 | ASPDAC | A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio. | Hong Phuc Ninh, Takashi Moue, Takashi Kurashina, Kenichi Okada, Akira Matsuzawa |
| 2008 | ASPDAC | Small-area CMOS RF distributed mixer using multi-port inductors. | Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu |
| 2008 | ISCAS | Design space exploration of low-phase-noise LC-VCO using multiple-divide technique. | Shoichi Hara, Takeshi Ito, Kenichi Okada, Akira Matsuzawa |
| 2007 | ASPDAC | Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation. | Satoshi Fukuda, D. Kawazoe, Kenichi Okada, Kazuya Masu |
| 2007 | ASPDAC | A Wideband CMOS LC-VCO Using Variable Inductor. | Kazuma Ohashi, Yusaku Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu |
| 2007 | ASPDAC | A Multi-Drop Transmission-Line Interconnect in Si LSI. | Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu |
| 2006 | ISCAS | Reconfigurable CMOS low noise amplifier for self compensation. | D. Kawazoe, Hirotaka Sugawara, Tatsuya Ito, Kenichi Okada, Kazuya Masu |
| 2005 | ASPDAC | Evaluation of on-chip transmission line interconnect using wire length distribution. | Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu |
| 2005 | ASPDAC | A dynamic reconfigurable RF circuit architecture. | Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu |
| 2004 | DATE | ULSI Interconnect Length Distribution Model Considering Core Utilization. | Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu |
| 2003 | ASPDAC | A statistical gate delay model for intra-chip and inter-chip variabilities. | Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera |
| 2003 | ISCAS | Statistical modeling of gate-delay variation with consideration of intra-gate variability. | Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera |
| 2000 | ISCAS | Statistical modeling of device characteristics with systematic fluctuation. | Kenichi Okada, Hidetoshi Onodera |