Kimiyoshi Usami
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
23
Venues
7
Active years
1990–2015
Best venue rank
A*
Where they publish
Papers
23 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | ISLPED | An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET. | Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano |
| 2014 | ASPDAC | Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. | Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura |
| 2014 | DATE | Design and evaluation of fine-grained power-gating for embedded microprocessors. | Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura |
| 2013 | FPL | Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. | Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura |
| 2012 | ASPDAC | A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. | Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano |
| 2012 | FPL | CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. | Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura |
| 2011 | ASPDAC | Geyser-2: The second prototype CPU with fine-grained run-time power gating. | Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo |
| 2011 | ISLPED | On-chip detection methodology for break-even time of power gated function units. | Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura |
| 2010 | ASPDAC | Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. | Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo |
| 2009 | VLSID | Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. | Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura |
| 2008 | DATE | Power Gating for Ultra-low Leakage: Physics, Design, and Analysis. | Jerry Frenkil, Ken Choi, Kimiyoshi Usami |
| 2008 | ICCD | A fine-grain dynamic sleep control scheme in MIPS R3000. | Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura |
| 2007 | ASPDAC | Overview on Low Power SoC Design Technology. | Kimiyoshi Usami |
| 2006 | ASPDAC | Delay modeling and static timing analysis for MTCMOS circuits. | Naoaki Ohkubo, Kimiyoshi Usami |
| 2006 | ICCD | A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. | Kimiyoshi Usami, Naoaki Ohkubo |
| 2002 | ISLPED | Automated selective multi-threshold design for ultra-low standby applications. | Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa |
| 2000 | ASPDAC | Low-power design methodology and applications utilizing dual supply voltages. | Kimiyoshi Usami, Mutsunori Igarashi |
| 2000 | DAC | Function-level power estimation methodology for microprocessors. | Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak |
| 1998 | ASPDAC | A Clock-Gating Method for Low-Power LSI Design. | Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi |
| 1998 | DAC | Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. | Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda |
| 1997 | ISLPED | A low-power design method using multiple supply voltages. | Mutsunori Igarashi, Kimiyoshi Usami, Kazutaka Nogami, Fumihiro Minami, Yukio Kawasaki, Takahiro Aoki, Midori Takano, Chiharo Mizuno, Takashi Ishikawa, Masahiro Kanazawa, Shinji Sonoda, Makoto Ichida, Naoyuki Hatanaka |
| 1995 | ISLPED | Clustered voltage scaling technique for low-power design. | Kimiyoshi Usami, Mark Horowitz |
| 1990 | DAC | Datapath Generator Based on Gate-Level Symbolic Layout. | Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori |